
`define Q_cal 6
`define WIDTH_LLR 768
`define WIDTH_CODE 128
`define WIDTH_CODE_MUL2 256
`define NUM_PTR_BIT 7


`timescale 1ns/1ps
`include "uvm_macros.svh"
import uvm_pkg::*;
`include "my_transaction.sv"
`include "my_driver.sv"


`include "my_model.sv"
`include "my_monitor.sv"
`include "my_sequence.sv"
`include "my_sequencer.sv"
`include "my_agent.sv"
`include "my_scoreboard.sv"
`include "my_env.sv"
`include "assert_to_bind.sv"




module top_tb;
reg clk;
reg rst_n;
reg [383:0] polar_enc_data_in;
reg polar_rate_sel;

wire polar_enc_done;
wire [1023:0] polar_enc_data_out;
reg polar_enc_start;

POLAR_ENC POLAR_ENC_inst
(
.clk(clk),
.rst_n(rst_n),
.polar_enc_start(polar_enc_start),
.polar_enc_done(polar_enc_done),

.polar_enc_data_in(polar_enc_data_in),
.polar_rate_sel(polar_rate_sel),
.polar_enc_data_out(polar_enc_data_out)
);

//assert
bind POLAR_ENC assert_encoder assert_encoder_inst(.*);

//top_uvm top_uvm_inst();
initial begin
    // my_driver drv;
    // drv = new("drv", null);
    // drv.main_phase(null);
    // $finish();

    run_test("my_env");
end


initial begin
    clk = 0;
    forever begin
    #2 clk =~clk;
    end
end

initial begin
    rst_n = 1'b0;
    #4;
    rst_n = 1'b1;

end

endmodule


// program top_uvm;

// initial begin
//     // my_driver drv;
//     // drv = new("drv", null);
//     // drv.main_phase(null);
//     // $finish();

//     run_test("my_env");
// end

// endprogram